LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.dec_pkg.all;

entity ram_f is
port(		clock1 	:in std_ulogic;
			reset1  	:in std_ulogic;
			write1  	:in std_ulogic;
			read1   	:in std_ulogic;
			en1     	:in std_ulogic;
			data1   	:in word32;
			addr1   	:in std_ulogic_vector(7 downto 0);
			clock2  	:in std_ulogic;
			reset2  	:in std_ulogic;
			write2  	:in std_ulogic;
			read2   	:in std_ulogic;
			en2     	:in std_ulogic;
			data2   	:out word16;
			addr2   	:in std_ulogic_vector(8 downto 0)
			);
end ram_f;

ARCHITECTURE beh OF ram_f IS 

component rd256x32mux4 is
port ( 
	QA: out std_logic_vector(31 downto 0);
	QB: out std_logic_vector(31 downto 0);
	CLKA: in std_logic;
	CENA: in std_logic;
	WENA : in std_ulogic;
	WENB : in std_ulogic; 
	BWENA: in std_logic_vector(31 downto 0);
	AA: in std_logic_vector(7 downto 0);
	DA: in std_logic_vector(31 downto 0);
	CLKB: in std_logic;
	CENB: in std_logic;
	BWENB: in std_logic_vector(31 downto 0);
	AB: in std_logic_vector(7 downto 0);
	DB: in std_logic_vector(31 downto 0)
    );
  end component;
    signal cena ,cenb:std_logic;
signal da,db,qa,qb ,bwena,bwenb:std_logic_vector(31 downto 0);
signal aa , ab:std_logic_vector(7 downto 0);
signal tt :std_ulogic_vector(8 downto 0);
signal wena ,wenb :std_logic_vector(1 downto 0);
begin
   cena <= not en1 ;
   wena(0) <= not write1 ;
   wena(1) <= not write1 ;
   da <= std_logic_vector(data1);
   cenb <= not en2 ;
   wenb(0) <= read2;
   wenb(1) <= read2;
   db <= (others => '0');
   aa <= std_logic_vector(addr1);
   ab <= std_logic_vector(addr2(8 downto 1));
   process(clock2)
   begin 
	   if clock2'event  and clock2 = '1' then 
                  tt <= addr2;
	  end if;
  end process;
  process(tt,qb)
  begin 
	  if tt(0) = '0' then 
		  data2 <= std_ulogic_vector(qb(15 downto 0));
	  else
		  data2 <= std_ulogic_vector(qb(31 downto 16));
	  end if;
  end process;
  bwena(31 downto 16) <= wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) & wena(1) ;
  bwena(15 downto 0)  <= wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) & wena(0) ;
  bwenb(31 downto 16) <= wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) & wenb(1) ;
  bwenb(15 downto 0)  <= wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) & wenb(0) ;
  u1:rd256x32mux4 port map
  (
      qb => qb ,
      clka => clock1 ,
      cena => cena,
      bwena => bwena,
      wena => wena(0),
      wenb => wenb(0),
      aa => aa,
      da => da,
      clkb => clock2,
      cenb => cenb,
      bwenb => bwenb,
      ab => ab,
      db => db
  );

end Beh;
